1. Field of the Invention
This invention relates to generating a clock signal and more particularly using a MEMS oscillator and digital locked loop to generate the clock signal.
2. Description of the Related Art
FIG. 1 illustrates one approach for generating a clock signal having a desired frequency using a fractional-N synthesizer 101 to generate to the desired frequency. A frequency setting is supplied to the sigma delta modulator 103 that generates a divide signal 105 for the divider 107. The use of the fractional-N synthesizer allows the generated frequency (out(t)) to have a non-integer relationship with the reference frequency (ref(t)).